Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit

ABSTRACT

Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of pending U.S. application Ser. No.11/333,997 filed on Jan. 18, 2006, the disclosure of which isincorporated herein by reference.

FIELD OF THE INVENTION

This invention relates generally to integrated circuits, and moreparticularly to techniques for utilizing sidewall spacer features toform magnetic tunnel junctions in integrated circuits.

BACKGROUND OF THE INVENTION

Magnetic memory devices, such as magnetic random access memory (MRAM)devices, use magnetic memory cells to store information. Information isstored in a magnetic memory cell as the orientation of the magnetizationof a free layer in the magnetic memory cell as compared to theorientation of the magnetization of a fixed or pinned layer in thememory cell. The magnetization of the free layer may be orientedparallel or anti-parallel to the fixed layer, representing either alogic “0” or a logic “1.” One type of memory cell, a magnetic tunneljunction (MTJ), comprises a free layer and a fixed layer separated by athin dielectric barrier (a tunnel barrier), which typically comprisesaluminum oxide. The resistance of the memory cell depends on thedirection of magnetization of the free layer relative to the directionof magnetization of the fixed layer. Thus, the state of the cell can besensed by measuring its resistance.

Reactive ion etching (RIE) is commonly used in MRAM processing as ameans of patterning MTJ features. In RIE, reactive gases are ionized andaccelerated towards the substrate. These reactive gases play two roles.They sputter the material from the surface, as well as chemically reactwith the material, thereby producing reaction products that are volatileand can be pumped away.

Because the etching medium is a flux of ions directed towards thesubstrate, RIE is predominantly anisotropic, meaning that etching occurspreferentially in the direction normal to the substrate. This translatesinto an etch rate on surfaces perpendicular to the substrate that ismuch lower than the etch rate on surfaces parallel to the substrate. Asa result, redeposition of etching byproducts may occur, particularly onthe sidewalls of vertical features where the etch rate is relativelylow.

Such byproduct redeposition is especially problematic in producing MRAMcircuitry. The etching byproducts formed when etching MTJ features areextremely difficult or impractical to remove without using methods thatalso cause harm to the sensitive film stack that makes up the etcheddevice itself. As a result, redeposition of etching byproducts remains amajor source of yield reduction in MRAM processing.

It is known that tapering an etched feature can result in increasedsputter yield at the feature's sidewalls, and, thereby, reduceredeposition. The difficulty, however, lies in finding a reliable andreproducible way of forming such a taper. Two techniques are known inthe art. In a first technique, the RIE chemistry is adjusted bybalancing the rates of anisotropic physical sputtering, isotropicchemical etching, and byproduct redeposition. However this balancingprocess is complex, and the balance of these three components is highlysensitive to the condition of the etch tool.

In a second technique, a masking layer is first deposited on the filmstack and patterned such that the masking layer can act as a hard maskduring the etching of the underlying film stack. The masking layer isthen physically sputtered so that its corners are eroded, therebycreating a taper in the masking layer which can subsequently betranslated into the film stack. Nevertheless, because of the possibilityof damage to the underlying film stack, the physical sputtering of themasking layer is usually limited. This frequently means that lowerreaches of the masking layer cannot be tapered sufficiently. As aresult, the redeposition of etching byproducts is frequently stillproblematic when subsequently etching the remainder of the film stack.

Accordingly, there is a need for a method of forming MTJ features inMRAM integrated circuits that is both more reliable and morereproducible than those currently known in the art, and does not sufferfrom one or more problems exhibited by conventional MTJ processingmethodologies.

SUMMARY OF THE INVENTION

The present invention addresses the above-identified needs by providinga novel method for reliably and reproducibly forming MTJs. An embodimentof the invention achieves this, at least in part, by the use of sidewallspacer features during the processing of the film stack. Advantageously,these sidewall spacer features create both a characteristic taperedmasking feature as well as an encapsulating layer for protecting aportion of the film stack during subsequent processing steps. Moreover,as an added benefit, the sidewall spacer features may, under certaincircumstances, be left in place and used as vertical contacts to higherlevels of metallization.

In accordance with an aspect of the invention, a method of forming MTJfeatures in integrated circuits comprises forming a film stack whereinthe film stack comprises one or magnetic materials. After forming thefilm stack, one or more trenches are formed in the film stack such thatthe sidewalls of the trenches are substantially vertical. Next, a spacerlayer is deposited on the film stack. The spacer layer is subsequentlyetched so that the spacer layer only remains on the sidewalls of thetrenches in the film stack. The film stack is subsequently furtheretched utilizing the etched spacer layer as a mask.

In an illustrative embodiment, a film stack includes a lower magneticlayer, dielectric layer, upper magnetic layer and a masking layer. Inprocessing this film stack, trenches with substantially verticalsidewalls are first formed in the masking layer. Next, sidewall spacerfeatures are formed on the sidewalls of these trenches utilizing easilycontrolled deposition and etching techniques. These sidewall spacerfeatures have characteristic tapered profiles. Subsequently, with thepatterned masking layer and sidewall spacer features acting as masks,the remainder of the film stack is etched leading to a tapered filmstack profile. Redeposition of etching byproducts is thereby reduced,resulting in improved MRAM processing yield.

These and other features and advantages of the present invention willbecome apparent from the following detailed description which is to beread in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1G show sectional views of MTJ features during various statesof processing in accordance with a first illustrative embodiment of theinvention.

FIGS. 2A-2F show sectional views of MTJ features during various statesof processing in accordance with a second illustrative embodiment of theinvention.

FIG. 3 shows a sectional view of a MTJ feature in accordance with athird illustrative embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

This invention will be illustrated herein in conjunction with exemplarymethods for forming MTJ features in integrated circuitry. It should beunderstood, however, that the invention is not limited to the particularmaterials, film layers and processing steps shown and described herein.Modifications to the illustrative embodiments will become apparent tothose skilled in the art.

Particularly with respect to processing steps, it is emphasized that thedescriptions provided herein are not intended to encompass all of theprocessing steps which may be required to successfully form a functionaldevice. Rather, certain processing steps which are conventionally usedin forming integrated circuit devices, such as, for example, wetcleaning and annealing steps, are purposefully not described herein foreconomy of description. However one skilled in the art will readilyrecognize those processing steps omitted from this generalizeddescription. Moreover, details of the process steps used to fabricatesuch semiconductor devices may be found in a number of publications, forexample, S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era,Volume 1, Lattice Press, 1986 and S. M. Sze, VLSI Technology, SecondEdition, McGraw-Hill, 1988, both of which are incorporated herein byreference.

It should also be understood that the various layers and/or regionsshown in the accompanying figures are not drawn to scale, and that oneor more semiconductor layers and/or regions of a type commonly used insuch integrated circuits may not be explicitly shown in a given figurefor ease of explanation. This does not imply that the semiconductorlayers and/or regions not explicitly shown are omitted from the actualintegrated circuit.

FIGS. 1A-1G show sectional views of MTJ features during various statesof processing in accordance with a first illustrative embodiment of theinvention. FIG. 1A shows a film stack after deposition of the layersthat will eventually form the data storage portion of the MTJ features.For illustrative purposes, the film stack is shown to consist of a lowermagnetic layer 110 and an upper magnetic layer 120. A thin dielectriclayer 130 lies in between the magnetic layers 110, 120, and acts as atunneling barrier in the MTJ device.

Each magnetic layer 110, 120 may further comprise a number of sublayers.These sublayers may be formed from many different materials and mayserve various functions such as, but not limited to, acting as barrierlayers, seed layers, antiferromagnetic layers, coupling layers andferromagnetic layers. Desikan et al., for example, describes a MTJ witha lower magnetic layer comprising five sublayers formed of cobalt/iron,nickel/iron, manganese/iron, platinum and tungsten, respectively.Desikan et al., On-chip MRAM as a High-Bandwidth Low Latency Replacementfor DRAM Physical Memories, Tech Report TR-02-47, Dept. of ComputerSciences, University of Texas, September 2002. The upper magnetic layerin the same device comprises three sublayers formed of nickel/iron,cobalt/iron and platinum, respectively. Id. The dielectric barrier isaluminum oxide. Id. For illustrative purposes herein, only the uppermagnetic layer 120 is shown to further comprise three sublayers, moreparticularly, a lower magnetic sublayer 122, a coupling sublayer 124,and an upper magnetic sublayer 126. Lower magnetic layer 110 is shown asa solid object in the figures for simplicity of illustration even thoughit too will typically comprise a plurality of sublayers.

One skilled in the art will recognize the functions of the magneticlayers 110, 120 and the dielectric layer 130 in a MTJ. Briefly, one ofthe magnetic layers, which may be referred to as a fixed magnetic layer,has a magnetic polarization that is pinned in a fixed direction whilethe polarization of the other magnetic layer, which may be referred toas a free magnetic layer, has a magnetic polarization that is alignedeither parallel or antiparallel to the fixed magnetic layer. Theresistance of a memory cell employing the MTJ storage element will beeither low or high depending on the relative polarization (parallel orantiparallel) of the free magnetic layer relative to the fixed magneticlayer. To provide a write capability, an applied magnetic field canswitch the polarization of the free magnetic layer with respect to thefixed magnetic layer. In a typical MRAM array, orthogonal lines (i.e.,bitlines and wordlines) pass under and over the MTJ, carrying currentthat produces the switching field. The MTJ is designed so that its logicstate will not be changed when current is applied to just one line, butwill always be written when current is flowing through both lines thatcross at the selected device.

Techniques for depositing metal layers include, but are not limited to,sputter deposition, evaporation, chemical vapor deposition (CVD) andelectroplating. Background on these techniques and others is providedin, for example, R. F. Bunshah, Handbook of Deposition Technologies forFilms and Coatings, Second Edition, Noyes Publishing, 1994, which isincorporated herein by reference. However, MTJ stack deposition has somespecial requirements that are different from those normally associatedwith, for example, multilevel metallization in semiconductor devices.The most important requirements, among others, include precisethin-layer controllability down to 0.01 nm, excellent materialuniformity across-wafer and smooth interface morphology. Moreover, thenecessity of controlling the magnetic properties of the ferromagneticmaterials also imposes special requirements on the deposition process.For example, most ferromagnetic materials have an inherent magneticanisotropy that is related to ordering on an atomic scale. Suchanisotropic behavior may affect the switching behavior of the material.Importantly, the direction of this anisotropy can be set duringdeposition of the layer by applying a uniform magnetic field across thewafer.

Because of these special requirements, the deposition of theferromagnetic metals for the MTJ film stack will preferably beaccomplished using sputter deposition techniques. In sputter deposition,ions are generated and directed at a target formed of the materialintended to be deposited. The ions knock off target atoms which aretransported to the substrate where they condense and form a film.Sputter deposition tends to produce extremely uniform metal films inboth composition and thickness. Moreover, some commercially availablesputter deposition equipment includes the ability to expose thesubstrate to a uniform magnetic field during deposition.

With reference to FIG. 1B, processing of the MTJ features is continuedby the deposition of a masking layer 140 on an upper surface of uppermagnetic layer 120. For compatibility with subsequent processing steps,the masking layer 140 is preferably formed of a refractory material suchas, but not limited to, tantalum nitride and titanium nitride. However,one skilled in the art will recognize that any suitable material may beused and still fall within the scope of the invention. A masking layercomprising refractory materials will preferably be formed by sputterdeposition.

Next, photolithography is used to define those regions of the integratedcircuit where MTJ features are intended. FIG. 1C shows a layer ofphotoresist 150 deposited on top of the masking layer 140 and patternedusing commonly available photolithographic techniques. Subsequently,with the developed photoresist 150 in place, the masking layer 140 isexposed to an anisotropic etching process, preferably RIE, so thattrenches are formed in the masking layer 140. The patterned maskinglayer 140 is shown in FIG. 1D after the photoresist 150 is stripped.

In accordance with an aspect of the invention, the sidewalls of thetrenches formed in the masking layer 140 are substantially vertical,meaning that they are substantially perpendicular to the upper surfaceof a substrate on which the MTJ stack is formed. Advantageously, theformation of trenches in refractory metal layers with vertical sidewallsis generally considered less demanding from a processing standpoint thanforming trenches with taper angles that are reproducible across-waferand from wafer-to-wafer. RIE reactants may include, but are not limitedto, triflouromethane, tetraflouromethane and tetrachlorosilane.

In accordance with another aspect of the invention, a spacer layer 160is next conformally deposited on the exposed surfaces of the MTJ filmstack, as shown in FIG. 1E. In this illustrative embodiment, the spacerlayer 160 is preferably composed of silicon nitride or silicon dioxide.Nonetheless, other suitable materials may be used and still fall withinthe scope of the invention. Silicon nitride deposition for the spacerlayer 160 is preferably performed by CVD with silane and ammonia as thereactants. Silicon dioxide deposition is preferably performed by CVDwith silane and oxygen, or tetraethoxyorthosilicate (TEOS), as thereactants. Such CVD deposition techniques generally have excellentconformality and gap-filling characteristics.

After the spacer layer 160 is formed, it is anisotropically etched toform sidewall spacer features by an etching process which does not etch,or only slowly etches, the patterned masking layer 140 and the uppermagnetic layer 120. Such an etching step is preferably performed by RIE.The directional nature of the RIE process leaves sidewall spacerfeatures, represented collectively by sidewall spacer feature 160S, onthe sidewalls of each of the vertical trenches in the patterned maskinglayer 140, but substantially removes any spacer layer material 160 fromthe horizontal surfaces of the film stack. In this step, the profile ofthe sidewalls of the trenches in the masking layer 140 is critical. Ifthe sidewalls are not substantially vertical, the spacer layer 160 onthe sidewalls of the trenches will have a higher etch rate during thesidewall spacer RIE step, and consequently will be thinned to a greaterdegree than would be the case if the sidewalls were substantiallyvertical.

Sidewall spacer features like those just described are used extensivelyin semiconductor processing in applications different from thosedescribed herein. For example, silicon nitride sidewall spacer featuresare frequently used in association with a gate stack inmetal-oxide-semiconductor field effect transistors to both protect thesidewalls of the gate stack and to act as self-aligned masks during ionimplantation. In accordance with an advantage of the invention, sidewallspacer features 160S formed using the foregoing processing steps arereadily formed with a characteristic tapered profile. Furthermore,because these tapered features are formed using a combination ofwell-controlled and well-characterized processing steps (e.g.,dielectric film deposition and dielectric RIE), the size and profile ofthe sidewall spacer features 160S tends to be extremely reproducible.

To complete the patterning of the MTJ features in accordance with thefirst illustrative embodiment, the MTJ film stack is etchedanisotropically, preferably by RIE, with the patterned masking layer 140and sidewall spacer features 160S in place. The results of this step areshown in FIG. 1G. The RIE process is performed in such a way that itselectively etches the magnetic layers 110, 120 and the dielectric layer130 while not etching, or only slowly etching, the patterned maskinglayer 140 and the sidewall spacer features 160S. In this way, thepatterned masking layer 140 and sidewall spacer features 160S act aswhat is commonly referred to as a hard mask. Such a RIE process can, forexample, be accomplished by using reactants comprising chlorine.

In accordance with an advantage of the invention, the tapered profile ofthe sidewall spacer features 160S results in the underlying MTJ featuresalso having a tapered profile. This phenomenon occurs, at least in part,because the sidewall spacer features 160S are progressively erodedduring the RIE processing by sputtering. This effectively means that theholes in the masking layers through which RIE reactants are etching theMTJ features slowly expand as the etching process proceeds. A taperedMTJ feature profile is thereby achieved, along with its resultantreduction in etching byproduct redeposition. Higher processing yield isthus obtained by using methods in accordance with this invention.

Alternatively, in accordance with a second illustrative processembodiment, sidewall spacer features may be used to allow a portion ofthe MTJ film stack to be processed while a different portion remainsencapsulated and unmodified. Such an embodiment is illustrated in FIGS.2A-2F, wherein like reference numerals denote identical or equivalentstructural elements. FIG. 2A shows the MTJ film stack with a patternedmasking layer 140 in place. The processing up to this point ispreferably identical to that described above with respect to FIGS.1A-1D. At this point in the process, however, the upper magneticsublayer 126 in the upper magnetic layer 120 is etched, preferably byRIE, using the patterned masking layer 140 as a hard mask. In accordancewith an aspect of the invention, the etching is accomplished such thatthe trench formed in the patterned masking layer 140 and the uppermagnetic sublayer 126 is substantially vertical. This vertical profilewill, as above, facilitate the formation of sidewall spacer features inlater processing.

It is noted that the RIE process described in the previous step isillustrative and need not necessarily etch just the upper magnetic layer126 as shown in the figure to fall within the scope of the invention.Alternatively, the etch may be designed to stop directly on the barrierlayer 130 or on the lower magnetic layer 110, or the etch may stoppartially through the barrier layer or lower magnetic layer. Moreover,the etch may be designed to stop on any given sublayer within the upperand lower magnetic layers 110, 120. Such variations will depend on theparticular application, and will be apparent to one skilled in the artin light of the illustrative embodiments described herein.

In subsequent processing, a spacer layer 260 is deposited on the exposedupper surfaces of the MTJ film stack, preferably by CVD, to fill thetrenches formed in the masking layer 140 and the upper magnetic sublayer126. The spacer layer 260 is then anisotropically etched, preferably byRIE, to form sidewall spacer features, collectively represented bysidewall spacer feature 260S, on the sidewalls of the trenches. This isshown in FIG. 2D. In the next processing step, the remainder of theexposed MTJ film stack is etched, preferably by RIE. In this case, theetch process will be masked by the patterned masking layer 140 and thesidewall spacer features 260S, as it was in the first embodimentdescribed above. The result of such an etch step is shown in FIG. 2E.

Advantageously, at this point in the process, the upper portion of thefilm stack, here the upper magnetic sublayer 126, is entirelyencapsulated by the sidewall spacer features 260S and the patternedmasking layer 140. This allows the exposed portion of the film stack tobe further processed while the encapsulated upper region remains intactand unmodified.

Moreover, it can be seen that the process steps illustrated in FIGS.2A-2E are capable of forming a MTJ film stack wherein an upper portionof the film stack has a narrower width than the bottom portion of thefilm stack. In the particular illustrated embodiment shown in thefigures, for example, the encapsulated upper magnetic sublayer 126 inthe upper magnetic layer 120 has a width that is narrower than theremainder of the MTJ film stack. It will be recognized, however, thatthe particular layer or sublayer at which the width change occurs caneasily be adjusted by stopping the RIE process illustrated in FIG. 2B atdifferent places in the film stack. For example, rather than having thisRIE step etch through the upper magnetic sublayer 126 and stop on thecoupling layer 124 in the upper magnetic layer 120, this RIE step couldbe designed to etch through the entirety of the upper magnetic layer 120and stop on the dielectric layer 130. After processing analogous to thesteps shown in FIGS. 2C and 2D, the resultant MTJ would, in this case,have an upper magnetic layer 120 that, in its entirety, is narrower thanthe dielectric layer 130 and the lower magnetic layer 110.

These width changes may be advantageous for a number of reasons, bothfrom design and processing standpoints. From a design standpoint,magnetic layers and sublayers of differing widths may allow the designerto fine tune the magnetic interactions between the different magneticlayers, especially those interactions occurring at the edges of thedevice. From a processing standpoint, the additional width in thebottommost layers allows dimensional changes from various subsequentprocessing steps to be compensated for. For example, thermally oxidizingor wet chemical etching the lower exposed portion of the MTJ film stackwill typically consume some of the width of those layers. Biasing theexposed portion to a larger width than the encapsulated portion usingthe sidewall spacer process described above allows this kind of processbias to be compensated for such that after the subsequent processing isperformed, the encapsulated and exposed portions of the MTJ film stackhave approximately the same width. The result of such subsequentprocessing is shown in FIG. 2F.

Additionally, or alternatively, in a third illustrative embodiment, thesidewall spacer features may be left in place and used as a self-alignedvertical contact from a MTJ feature to higher metallization levels. Suchan implementation is shown in FIG. 3. In this case, the sidewall spacerfeatures, represented collectively by sidewall spacer feature 360S, aremade of an electrically conductive material rather than a dielectricmaterial. The conductive material could, for example, comprise tantalumnitride or titanium nitride. After following steps analogous to thoseshown in FIGS. 2A-2E, the patterned masking layer 140 and sidewallspacer features 360S are left in place rather than removed. In furtherprocessing steps, an interlevel dielectric 370 is deposited around thestructure and a metal feature 380 is formed therein according tocommonly used semiconductor fabrication techniques. The metal feature380 is formed such that it is in electrical and physical contact withthe conducting sidewall spacer features 360S.

Advantageously, these vertical contacts provide a reliable andrelatively easy way to form an electrical contact between upper magneticlayer 120 and higher levels of metallization. Without the use of thesefeatures, a sufficient number of discrete contacts would have to beformed and landed on the upper magnetic layer 120. Forming of thesediscrete contacts would typically require the use of at least anadditional photolithographic mask and additional etching steps, therebyadding substantial cost and complexity to the manufacturing process.This cost and complexity is, in this way, avoided by the use of methodswithin the scope of this invention.

The processes described herein may be implemented to form an integratedcircuit. In forming integrated circuits, a plurality of identical die istypically fabricated in a repeated pattern on a surface of ansemiconductor wafer. Each die includes a device formed by the methodsdescribed herein, and may include other structures or circuits. Theindividual die are cut or diced from the wafer, then packaged as anintegrated circuit. One skilled in the art would know how to dice wafersand package die to produce integrated circuits. Integrated circuits somanufactured are considered part of this invention.

Although illustrative embodiments of the present invention have beendescribed herein with reference to the accompanying figures, it is to beunderstood that the invention is not limited to those preciseembodiments, and that various other changes and modifications may bemade therein by one skilled in the art without departing from the scopeof the appended claims.

1. A method of forming a magnetic tunnel junction, the method comprisingthe steps of: forming a film stack, the film stack comprising one ormore magnetic layers; forming one or more trenches in the film stack,sidewalls of the one or more trenches being substantially vertical;forming a spacer layer at least partially on top of the film stack;etching the spacer layer such that portions of the spacer layer onlyremain on the sidewalls of the one or more trenches in the film stack;and etching at least a portion of the film stack utilizing the etchedspacer layer as a mask.
 2. The method of claim 1, wherein at least oneof the one or more magnetic layers comprises a ferromagnetic material.3. The method of claim 1, wherein the film stack comprises at least oneof cobalt, nickel, iron, and a combination thereof.
 4. The method ofclaim 1, wherein the film stack comprises one or more masking layers,portions of the one or more masking layers acting as a mask during thestep of etching at least a portion of the film stack.
 5. The method ofclaim 3, wherein at least one of the one or more masking layerscomprises a refractory material.
 6. The method of claim 1, wherein thestep of forming the one or more trenches in the film stack is performedusing photolithography.
 7. The method of claim 1, wherein the spacerlayer comprises a dielectric material.
 8. The method of claim 1, whereinthe spacer layer comprises an electrically conductive material.
 9. Themethod of claim 1 wherein the spacer layer comprises tantalum nitride ortitanium nitride.
 10. The method of claim 1 wherein the step ofdepositing the spacer layer is performed using chemical vapordeposition.
 11. The method of claim 1, wherein the step of etching thespacer layer is performed using substantially anisotropic etching. 12.The method of claim 1, wherein the step of etching the spacer layer isperformed using reactive ion etching.
 13. The method of claim 1, whereinthe step of etching at least a portion of the film stack utilizing theetched spacer layer as a mask is performed using substantiallyanisotropic etching.
 14. The method of claim 1, wherein the step ofetching at least a portion of the film stack utilizing the etched spacerlayer as a mask comprises using reactive ion etching.
 15. The method ofclaim 1, further comprising the step of wet chemical etching at least aportion of the film stack with the etched spacer layer in place.
 16. Themethod of claim 1, further comprising the step of thermally oxidizing atleast a portion of the film stack with the etched spacer layer in place.17. The method of claim 1, further comprising forming a metallizationfeature above at least a portion of the film stack, wherein the etchedspacer layer is operative to electrically connect the film stack to themetallization feature.
 18. A semiconductor wafer comprising a pluralityof integrated circuits, the plurality of integrated circuits comprisingone or more magnetic tunnel junctions formed at least in part by thesteps of: forming a film stack, the film stack comprising one or moremagnetic layers; forming one or more trenches in the film stack,sidewalls of the one or more trenches being substantially vertical;forming a spacer layer at least partially on top of the film stack;etching the spacer layer such that portions of the spacer layer onlyremain on the sidewalls of the one or more trenches in the film stack;and etching at least a portion of the film stack utilizing the etchedspacer layer as a mask.
 19. An integrated circuit comprising one or moremagnetic tunnel junctions, the one or more magnetic tunnel junctionsformed at least in part by the steps of: forming a film stack, the filmstack comprising one or more magnetic layers; forming one or moretrenches in the film stack, sidewalls of the one or more trenches beingsubstantially vertical; forming a spacer layer at least partially on topof the film stack; etching the spacer layer such that portions of thespacer layer only remain on the sidewalls of the one or more trenches inthe film stack; and etching at least a portion of the film stackutilizing the etched spacer layer as a mask.
 20. The integrated circuitof claim 19, wherein the integrated circuit comprises magnetic randomaccess memory circuitry.